Juried Engineering CD4011BE CD4011B CD4011 CMOS Quad 2-Input NAND Gate Breadboard-Friendly IC DIP-14 (Pack of 8)
Asin: B08GYQCNDQ | Model: CD4011BE | PartNumber: CD4011BE | Ean: 0799993468255 | UPC: 799993468255
As an Amazon Associate we earn a fee from qualifying purchases when you follow a link to Amazon from this page. We rank the products, but the links to Amazon are promotional.Buffered Inputs And Outputs, 100% Tested For Quiescent Current At 20 V.
Maximum Input Current Of 1 Μa At 18 V Over-Full Package Temperature Range; 100 Na At 18 V And 25°C, Noise Margin (Over Full Package Temperature Range: 1 V At Vdd = 5 V, 2 V At Vdd = 10 V, 2.5 At Vdd = 15 V.
Standardized Symmetrical Output Characteristics, 5-V, 10-V, And 15-V Parametric Ratings, Meets All Requirements Of Jedec Tentative Standard No. 13B, "Standard Specifications For Description Of "B" Series Cmos Devices".
Propagation Delay Time = 60 Ns (Typ.) At Cl = 50 Pf, Vdd = 10 V.
Features
- The CD4011B Quad 2 Input NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates
- Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
- Buffered inputs and outputs, 100% tested for quiescent current at 20 V
- Standardized symmetrical output characteristics, 5-V, 10-V, and 15-V parametric ratings, Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B Series CMOS Devices
- Maximum input current of 1 A at 18 V over-full package temperature range; 100 nA at 18 V and 25 C, Noise margin (over full package temperature range: 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 at VDD = 15 V
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Brand: Juried Engineering | Manufacturer: TI
See On Amazon Similar To Juried Engineering CD4011BE CD4011B CD4011
#1
Juried Engineering CD4071BE CD4071 CMOS Quad 2-Input OR Gate Breadboard-Friendly (1 Piece)
Asin: B07RJNS9VF | Model: C4071BE | PartNumber: C4071BE | Ean: 0719417816745 | UPC: 719417816745
Maximum Input Current Of 1 Μa At 18 V Over Full Package-Temperature Range; 100 Na At 18 V And 25°C.
5-V, 10-V, And 15-V Parametric Ratings.
Standardized, Symmetrical Output Characteristics.
100% Tested For Quiescent Current At 20 V.
Features
- Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25 C
- Standardized, symmetrical output characteristics
- 5-V, 10-V, and 15-V parametric ratings
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Brand: Juried Engineering | Manufacturer: TI
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CHIPNEW CD4011BE KIT
Asin: B0CPWJ54F9
Brand: CHIPNEW | Manufacturer: CHIPNEW
See On Amazon #3
Juried Engineering CD4043BE CD4043 CD4043 CMOS Quad NOR R/S Latch with 3-State Outputs Breadboard-Friendly IC DIP-16 (Pack of 5)
Asin: B08DHHW6SH | Model: CD4043BE | PartNumber: CD4043BE | Ean: 0799993465131 | UPC: 799993465131
Separate Set And Reset Inputs For Each Latch, Standardized Symmetrical Output Characteristics, Meets All Requirements Of Jedec Tentative Standard No. 13B, "Standard Specifications For Description Of 'B' Series Cmos Devices".
Example Applications: Holding Register In Multi-Register System, Four Bits Of Independent Storage With Output Enable, Strobed Register, General Digital Logic.
Nor And Nand Configurations, 100% Tested For Quiescent Current At 20 V, Maximum Input Current Of 1 Μa At 18 V Over Full Package Temperature Range; 100 Na At 18 V And 25°C.
3-State Outputs With Common Output Enable, 5-V, 10-V, And 15-V Parametric Ratings, Noise Margin (Over Full Package Temperature Range): 1 V At Vdd = 5 V, 2 V At Vdd = 10 V, 2.5 V At Vdd = 15 V.
Features
- The CD4043B types are quad cross-coupled 3-state CMOS NOR latches. Each latch has a separate Q output and individual SET and RESET inputs.
- 3-state outputs with common output ENABLE, 5-V, 10-V, and 15-V parametric ratings, Noise margin (over full package temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
- Separate SET and RESET inputs for each latch, Standardized symmetrical output characteristics, Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of 'B' Series CMOS Devices
- NOR and NAND configurations, 100% tested for quiescent current at 20 V, Maximum input current of 1 A at 18 V over full package temperature range; 100 nA at 18 V and 25 C
- Example Applications: Holding register in multi-register system, Four bits of independent storage with output ENABLE, Strobed register, General digital logic
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Juried Engineering CD4011BE CD4011B CD4011 CMOS Quad 2-Input NAND Gate Breadboard-Friendly IC DIP-14 (Pack of 3)
Asin: B08DFCVHXN | Model: CD4011BE | PartNumber: CD4011BE | Ean: 0799993464974 | UPC: 799993464974
Buffered Inputs And Outputs, 100% Tested For Quiescent Current At 20 V.
Maximum Input Current Of 1 Μa At 18 V Over-Full Package Temperature Range; 100 Na At 18 V And 25°C, Noise Margin (Over Full Package Temperature Range: 1 V At Vdd = 5 V, 2 V At Vdd = 10 V, 2.5 At Vdd = 15 V.
Standardized Symmetrical Output Characteristics, 5-V, 10-V, And 15-V Parametric Ratings, Meets All Requirements Of Jedec Tentative Standard No. 13B, "Standard Specifications For Description Of "B" Series Cmos Devices".
Propagation Delay Time = 60 Ns (Typ.) At Cl = 50 Pf, Vdd = 10 V.
Features
- The CD4011B Quad 2 Input NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates
- Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
- Buffered inputs and outputs, 100% tested for quiescent current at 20 V
- Standardized symmetrical output characteristics, 5-V, 10-V, and 15-V parametric ratings, Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B Series CMOS Devices
- Maximum input current of 1 A at 18 V over-full package temperature range; 100 nA at 18 V and 25 C, Noise margin (over full package temperature range: 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 at VDD = 15 V
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Brand: Juried Engineering | Manufacturer: TI
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Juried Engineering CD4043BE CD4043 CD4043 CMOS Quad NOR R/S Latch with 3-State Outputs Breadboard-Friendly IC DIP-16 (Pack of 10)
Asin: B011NAV9NC | Model: CD4043BE | PartNumber: CD4043BE | Ean: 0799993465148 | UPC: 799993465148
Separate Set And Reset Inputs For Each Latch, Standardized Symmetrical Output Characteristics, Meets All Requirements Of Jedec Tentative Standard No. 13B, "Standard Specifications For Description Of 'B' Series Cmos Devices".
Example Applications: Holding Register In Multi-Register System, Four Bits Of Independent Storage With Output Enable, Strobed Register, General Digital Logic.
Nor And Nand Configurations, 100% Tested For Quiescent Current At 20 V, Maximum Input Current Of 1 Μa At 18 V Over Full Package Temperature Range; 100 Na At 18 V And 25°C.
3-State Outputs With Common Output Enable, 5-V, 10-V, And 15-V Parametric Ratings, Noise Margin (Over Full Package Temperature Range): 1 V At Vdd = 5 V, 2 V At Vdd = 10 V, 2.5 V At Vdd = 15 V.
Features
- The CD4043B types are quad cross-coupled 3-state CMOS NOR latches. Each latch has a separate Q output and individual SET and RESET inputs.
- 3-state outputs with common output ENABLE, 5-V, 10-V, and 15-V parametric ratings, Noise margin (over full package temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
- Separate SET and RESET inputs for each latch, Standardized symmetrical output characteristics, Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of 'B' Series CMOS Devices
- NOR and NAND configurations, 100% tested for quiescent current at 20 V, Maximum input current of 1 A at 18 V over full package temperature range; 100 nA at 18 V and 25 C
- Example Applications: Holding register in multi-register system, Four bits of independent storage with output ENABLE, Strobed register, General digital logic
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Juried Engineering CD4011BE CD4011B CD4011 CMOS Quad 2-Input NAND Gate Breadboard-Friendly IC DIP-14 (1 Piece)
Asin: B08DFB5KZG | Model: CD4011BE | PartNumber: CD4011BE | Ean: 0799993464967 | UPC: 799993464967
Buffered Inputs And Outputs, 100% Tested For Quiescent Current At 20 V.
Maximum Input Current Of 1 Μa At 18 V Over-Full Package Temperature Range; 100 Na At 18 V And 25°C, Noise Margin (Over Full Package Temperature Range: 1 V At Vdd = 5 V, 2 V At Vdd = 10 V, 2.5 At Vdd = 15 V.
Standardized Symmetrical Output Characteristics, 5-V, 10-V, And 15-V Parametric Ratings, Meets All Requirements Of Jedec Tentative Standard No. 13B, "Standard Specifications For Description Of "B" Series Cmos Devices".
Propagation Delay Time = 60 Ns (Typ.) At Cl = 50 Pf, Vdd = 10 V.
Features
- The CD4011B Quad 2 Input NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates
- Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
- Buffered inputs and outputs, 100% tested for quiescent current at 20 V
- Standardized symmetrical output characteristics, 5-V, 10-V, and 15-V parametric ratings, Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B Series CMOS Devices
- Maximum input current of 1 A at 18 V over-full package temperature range; 100 nA at 18 V and 25 C, Noise margin (over full package temperature range: 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 at VDD = 15 V
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Brand: Juried Engineering | Manufacturer: TI
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Juried Engineering CD4075BE CD4075B CD4075 4075 CMOS Triple 3-Input OR Gate Breadboard-Friendly IC DIP-14 (Pack of 5)
Asin: B08DW6ZDNR | Model: CD4075BE | PartNumber: CD4075BE | Ean: 0799993465865 | UPC: 799993465865
100% Tested For Quiescent Current At 20 V, Standardized, Symmetrical Output Characteristics.
Noise Margin (Full Package-Temperature Range): 1 V At Vdd = 5 V, 2 V At Vdd = 10 V, 2.5 V At Vdd = 15 V, Meets All Requirements Of Jedec Tentative Standard No. 13B, "Standard Specifications For Description Of ’B’ Series Cmos Devices".
Maximum Input Current Of 1 Μa At 18 V Over Full Package-Temperature Range; 100 Na At 18 V And 25°C.
Medium-Speed Operation - Tplh, Tphl = 60 Ns (Typ.) At Vdd = 10 V, 5-V, 10-V, And 15-V Parametric Ratings.
Features
- The CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates
- Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V, 5-V, 10-V, and 15-V parametric ratings
- 100% tested for quiescent current at 20 V, Standardized, symmetrical output characteristics
- Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25 C
- Noise margin (full package-temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V, Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B Series CMOS Devices
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Brand: Juried Engineering | Manufacturer: TI
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Juried Engineering CD4043BE CD4043 CD4043 CMOS Quad NOR R/S Latch with 3-State Outputs Breadboard-Friendly IC DIP-16 (Pack of 20)
Asin: B08DHFYVFV | Model: CD4043BE | PartNumber: CD4043BE | Ean: 0799993465155 | UPC: 799993465155
Separate Set And Reset Inputs For Each Latch, Standardized Symmetrical Output Characteristics, Meets All Requirements Of Jedec Tentative Standard No. 13B, "Standard Specifications For Description Of 'B' Series Cmos Devices".
Example Applications: Holding Register In Multi-Register System, Four Bits Of Independent Storage With Output Enable, Strobed Register, General Digital Logic.
Nor And Nand Configurations, 100% Tested For Quiescent Current At 20 V, Maximum Input Current Of 1 Μa At 18 V Over Full Package Temperature Range; 100 Na At 18 V And 25°C.
3-State Outputs With Common Output Enable, 5-V, 10-V, And 15-V Parametric Ratings, Noise Margin (Over Full Package Temperature Range): 1 V At Vdd = 5 V, 2 V At Vdd = 10 V, 2.5 V At Vdd = 15 V.
Features
- The CD4043B types are quad cross-coupled 3-state CMOS NOR latches. Each latch has a separate Q output and individual SET and RESET inputs.
- 3-state outputs with common output ENABLE, 5-V, 10-V, and 15-V parametric ratings, Noise margin (over full package temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
- Separate SET and RESET inputs for each latch, Standardized symmetrical output characteristics, Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of 'B' Series CMOS Devices
- NOR and NAND configurations, 100% tested for quiescent current at 20 V, Maximum input current of 1 A at 18 V over full package temperature range; 100 nA at 18 V and 25 C
- Example Applications: Holding register in multi-register system, Four bits of independent storage with output ENABLE, Strobed register, General digital logic
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Brand: Juried Engineering | Manufacturer: TI
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Juried Engineering CD4042BE CD4042 CD4042 CMOS Quad Clocked 'D' Latch Breadboard-Friendly IC DIP-16 (Pack of 10)
Asin: B08DHG9RS3 | Model: CD4042BE | PartNumber: CD4042BE | Ean: 0799993465100 | UPC: 799993465100
Low Power Ttl Compatible, Standardized, Symmetrical Output Characteristics, 100% Tested For Quiescent Current At 20 V.
Meets All Requirements Of Jedec Tentative Standard No. 13B, "Standard Specifications For Description Of ’B’ Series Cmos Devices", Example Applications: Buffer Storage, Holding Register, General Digital Logic.
Maximum Input Current Of 1 Μa At 18 V Over Full Package-Temperature Range; 100 Na At 18 V And 25°C, 5-V, 10-V, And 15-V Parametric Ratings.
Clock Polarity Control, Q And Q Outputs, Common Clock, Noise Margin (Full Package-Temperature Range) = 1 V At Vdd = 5 V, 2 V At Vdd = 10 V, 2.5 V At Vdd = 15 V.
Features
- The CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit.
- Clock polarity control, Q and Q outputs, Common Clock, Noise margin (full package-temperature range) = 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
- Low power TTL compatible, Standardized, symmetrical output characteristics, 100% tested for quiescent current at 20 V
- Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25 C, 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B Series CMOS Devices, Example Applications: Buffer storage, Holding register, General digital logic
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Brand: Juried Engineering | Manufacturer: TI
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Juried Engineering CD4011BE CD4011B CD4011 CMOS Quad 2-Input NAND Gate Breadboard-Friendly IC DIP-14 (Pack of 10)
Asin: B08GY9QMVV | Model: CD4011BE | PartNumber: CD4011BE | Ean: 0799993468262 | UPC: 799993468262
Buffered Inputs And Outputs, 100% Tested For Quiescent Current At 20 V.
Maximum Input Current Of 1 Μa At 18 V Over-Full Package Temperature Range; 100 Na At 18 V And 25°C, Noise Margin (Over Full Package Temperature Range: 1 V At Vdd = 5 V, 2 V At Vdd = 10 V, 2.5 At Vdd = 15 V.
Standardized Symmetrical Output Characteristics, 5-V, 10-V, And 15-V Parametric Ratings, Meets All Requirements Of Jedec Tentative Standard No. 13B, "Standard Specifications For Description Of "B" Series Cmos Devices".
Propagation Delay Time = 60 Ns (Typ.) At Cl = 50 Pf, Vdd = 10 V.
Features
- The CD4011B Quad 2 Input NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates
- Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
- Buffered inputs and outputs, 100% tested for quiescent current at 20 V
- Standardized symmetrical output characteristics, 5-V, 10-V, and 15-V parametric ratings, Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B Series CMOS Devices
- Maximum input current of 1 A at 18 V over-full package temperature range; 100 nA at 18 V and 25 C, Noise margin (over full package temperature range: 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 at VDD = 15 V
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Brand: Juried Engineering | Manufacturer: TI
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Juried Engineering CD4075BE CD4075B CD4075 4075 CMOS Triple 3-Input OR Gate Breadboard-Friendly IC DIP-14 (Pack of 10)
Asin: B08DW5PY5N | Model: CD4075BE | PartNumber: CD4075BE | Ean: 0799993465872 | UPC: 799993465872
100% Tested For Quiescent Current At 20 V, Standardized, Symmetrical Output Characteristics.
Noise Margin (Full Package-Temperature Range): 1 V At Vdd = 5 V, 2 V At Vdd = 10 V, 2.5 V At Vdd = 15 V, Meets All Requirements Of Jedec Tentative Standard No. 13B, "Standard Specifications For Description Of ’B’ Series Cmos Devices".
Maximum Input Current Of 1 Μa At 18 V Over Full Package-Temperature Range; 100 Na At 18 V And 25°C.
Medium-Speed Operation - Tplh, Tphl = 60 Ns (Typ.) At Vdd = 10 V, 5-V, 10-V, And 15-V Parametric Ratings.
Features
- The CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates
- Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V, 5-V, 10-V, and 15-V parametric ratings
- 100% tested for quiescent current at 20 V, Standardized, symmetrical output characteristics
- Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25 C
- Noise margin (full package-temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V, Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B Series CMOS Devices
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Brand: Juried Engineering | Manufacturer: TI
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Juried Engineering CD4044BE CD4044B CD4044 CMOS Quad NAND R/S Latch with 3-State Outputs Breadboard-Friendly IC DIP-16 (Pack of 10)
Asin: B08DHSGDZF | Model: CD4044BE | PartNumber: CD4044BE | Ean: 0799993465186 | UPC: 799993465186
Separate Set And Reset Inputs For Each Latch, Standardized Symmetrical Output Characteristics, Meets All Requirements Of Jedec Tentative Standard No. 13B, "Standard Specifications For Description Of 'B' Series Cmos Devices".
Example Applications: Holding Register In Multi-Register System, Four Bits Of Independent Storage With Output Enable, Strobed Register, General Digital Logic.
Nor And Nand Configurations, 100% Tested For Quiescent Current At 20 V, Maximum Input Current Of 1 Μa At 18 V Over Full Package Temperature Range; 100 Na At 18 V And 25°C.
3-State Outputs With Common Output Enable, 5-V, 10-V, And 15-V Parametric Ratings, Noise Margin (Over Full Package Temperature Range): 1 V At Vdd = 5 V, 2 V At Vdd = 10 V, 2.5 V At Vdd = 15 V.
Features
- The CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs.
- 3-state outputs with common output ENABLE, 5-V, 10-V, and 15-V parametric ratings, Noise margin (over full package temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
- Separate SET and RESET inputs for each latch, Standardized symmetrical output characteristics, Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of 'B' Series CMOS Devices
- NOR and NAND configurations, 100% tested for quiescent current at 20 V, Maximum input current of 1 A at 18 V over full package temperature range; 100 nA at 18 V and 25 C
- Example Applications: Holding register in multi-register system, Four bits of independent storage with output ENABLE, Strobed register, General digital logic
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Brand: Juried Engineering | Manufacturer: TI
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Juried Engineering CD4075BE CD4075B CD4075 4075 CMOS Triple 3-Input OR Gate Breadboard-Friendly IC DIP-14 (1 Piece)
Asin: B08DW5LH75 | Model: CD4075BE | PartNumber: CD4075BE | Ean: 0799993465858 | UPC: 799993465858
100% Tested For Quiescent Current At 20 V, Standardized, Symmetrical Output Characteristics.
Noise Margin (Full Package-Temperature Range): 1 V At Vdd = 5 V, 2 V At Vdd = 10 V, 2.5 V At Vdd = 15 V, Meets All Requirements Of Jedec Tentative Standard No. 13B, "Standard Specifications For Description Of ’B’ Series Cmos Devices".
Maximum Input Current Of 1 Μa At 18 V Over Full Package-Temperature Range; 100 Na At 18 V And 25°C.
Medium-Speed Operation - Tplh, Tphl = 60 Ns (Typ.) At Vdd = 10 V, 5-V, 10-V, And 15-V Parametric Ratings.
Features
- The CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates
- Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V, 5-V, 10-V, and 15-V parametric ratings
- 100% tested for quiescent current at 20 V, Standardized, symmetrical output characteristics
- Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25 C
- Noise margin (full package-temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V, Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B Series CMOS Devices
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Brand: Juried Engineering | Manufacturer: TI
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Juried Engineering CD4042BE CD4042 CD4042 CMOS Quad Clocked 'D' Latch Breadboard-Friendly IC DIP-16 (Pack of 5)
Asin: B08DHMHJT7 | Model: CD4042BE | PartNumber: CD4042BE | Ean: 0799993465094 | UPC: 799993465094
Low Power Ttl Compatible, Standardized, Symmetrical Output Characteristics, 100% Tested For Quiescent Current At 20 V.
Meets All Requirements Of Jedec Tentative Standard No. 13B, "Standard Specifications For Description Of ’B’ Series Cmos Devices", Example Applications: Buffer Storage, Holding Register, General Digital Logic.
Maximum Input Current Of 1 Μa At 18 V Over Full Package-Temperature Range; 100 Na At 18 V And 25°C, 5-V, 10-V, And 15-V Parametric Ratings.
Clock Polarity Control, Q And Q Outputs, Common Clock, Noise Margin (Full Package-Temperature Range) = 1 V At Vdd = 5 V, 2 V At Vdd = 10 V, 2.5 V At Vdd = 15 V.
Features
- The CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit.
- Clock polarity control, Q and Q outputs, Common Clock, Noise margin (full package-temperature range) = 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
- Low power TTL compatible, Standardized, symmetrical output characteristics, 100% tested for quiescent current at 20 V
- Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25 C, 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B Series CMOS Devices, Example Applications: Buffer storage, Holding register, General digital logic
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Brand: Juried Engineering | Manufacturer: TI
See On Amazon #15
Juried Engineering CD4044BE CD4044B CD4044 CMOS Quad NAND R/S Latch with 3-State Outputs Breadboard-Friendly IC DIP-16 (Pack of 5)
Asin: B08DHJFLG4 | Model: CD4044BE | PartNumber: CD4044BE | Ean: 0799993465179 | UPC: 799993465179
Separate Set And Reset Inputs For Each Latch, Standardized Symmetrical Output Characteristics, Meets All Requirements Of Jedec Tentative Standard No. 13B, "Standard Specifications For Description Of 'B' Series Cmos Devices".
Example Applications: Holding Register In Multi-Register System, Four Bits Of Independent Storage With Output Enable, Strobed Register, General Digital Logic.
Nor And Nand Configurations, 100% Tested For Quiescent Current At 20 V, Maximum Input Current Of 1 Μa At 18 V Over Full Package Temperature Range; 100 Na At 18 V And 25°C.
3-State Outputs With Common Output Enable, 5-V, 10-V, And 15-V Parametric Ratings, Noise Margin (Over Full Package Temperature Range): 1 V At Vdd = 5 V, 2 V At Vdd = 10 V, 2.5 V At Vdd = 15 V.
Features
- The CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs.
- 3-state outputs with common output ENABLE, 5-V, 10-V, and 15-V parametric ratings, Noise margin (over full package temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
- Separate SET and RESET inputs for each latch, Standardized symmetrical output characteristics, Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of 'B' Series CMOS Devices
- NOR and NAND configurations, 100% tested for quiescent current at 20 V, Maximum input current of 1 A at 18 V over full package temperature range; 100 nA at 18 V and 25 C
- Example Applications: Holding register in multi-register system, Four bits of independent storage with output ENABLE, Strobed register, General digital logic
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Brand: Juried Engineering | Manufacturer: TI
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Juried Engineering CD4011BE CD4011B CD4011 CMOS Quad 2-Input NAND Gate Breadboard-Friendly IC DIP-14 (Pack of 20)
Asin: B08DF4JVRT | Model: CD4011BE | PartNumber: CD4011BE | Ean: 0799993464998 | UPC: 799993464998
Buffered Inputs And Outputs, 100% Tested For Quiescent Current At 20 V.
Maximum Input Current Of 1 Μa At 18 V Over-Full Package Temperature Range; 100 Na At 18 V And 25°C, Noise Margin (Over Full Package Temperature Range: 1 V At Vdd = 5 V, 2 V At Vdd = 10 V, 2.5 At Vdd = 15 V.
Standardized Symmetrical Output Characteristics, 5-V, 10-V, And 15-V Parametric Ratings, Meets All Requirements Of Jedec Tentative Standard No. 13B, "Standard Specifications For Description Of "B" Series Cmos Devices".
Propagation Delay Time = 60 Ns (Typ.) At Cl = 50 Pf, Vdd = 10 V.
Features
- The CD4011B Quad 2 Input NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates
- Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
- Buffered inputs and outputs, 100% tested for quiescent current at 20 V
- Standardized symmetrical output characteristics, 5-V, 10-V, and 15-V parametric ratings, Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B Series CMOS Devices
- Maximum input current of 1 A at 18 V over-full package temperature range; 100 nA at 18 V and 25 C, Noise margin (over full package temperature range: 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 at VDD = 15 V
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20pcs/lot CD4011 CD4011BE CD4011BCN DIP14
Asin: B07WF4195Z | Ean: 4814005093242
Brand: Deeoee | Manufacturer: Deeoee
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20pcs/lot CD4011 CD4011BE CD4011BCN DIP-14
Asin: B0D49XXX79
Brand: Generic | Manufacturer: Generic
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10pcs/lot CD4011BE CD4011 DIP-14
Asin: B0D49V35LD
Brand: Generic | Manufacturer: Generic
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